Synchronization Mode Four different modes may be defined under user control. The TRIG1 and TRIG2 signals may be used to trigger external events and to control the integration time. The Master clock is either external or internal clock. 8.1.1 Free Run Mode with Integration Time Setting The integration and readout periods start automatically and immediately after the previous period. The read-out time depends on pixel number and pixel rate. Note: 1. The integration time is set by the serial line and should be higher than the read-out time (otherwise it is adjusted to the readout time). Figure 8-1.

      Timing Diagram 8.1.2 Triggered Mode with Integration Time Setting The integration period starts immediately after the rising edge of TRIG1 input signal. The Integration time is set by the serial line. This integration period is immediately followed by a readout period. The read-out time depends on pixel number and the pixel rate. Table 8-1. Free Run Mode with Integration Time Setting Label Description Min Typ Max ti Integration time duration (1) – 13 ms tg Consecutive integration period gap (at maximum frequency) – 6 μs – tt Integration period stop to read-out start delay – 1 μs – Integration N Readout N-1 Readout N Integration N+1 tt ti tg Table 8-2. Triggered Mode with Integration Time Setting Label Description Min Typ Max ti Integration time duration 5 μs – 13 ms td TRIG1 rising to integration period start delay – 5.5 μs –    

      Trigger and Integration Time Controlled by One Input The integration period starts immediately after the falling edge of TRIG1 input signal, stops immediately after the rising edge of TRIG1 input signal, and is immediately followed by a readout period. The readout time depends on pixel number and pixel rate. Figure 8-3. Timing Diagram 8.1.4 Trigger and Integration Time Controlled by Two Inputs TRIG2 rising edge start the integration period. TRIG1 rising edge stop the integration period. This period is immediately followed by a readout period. tt Integration period stop to read-out start delay – 1 μs – ts Integration period stop to TRIG1 rising set-up time 4 μs – – th TRIG1 hold time (pulse high duration) 1 μs – – Table 8-2. Triggered Mode with Integration Time Setting (Continued) Label Description Min Typ Max Integration N Integration N+1 Readout N TRIG1 td ts th tt ti Table 8-3. Trigger and Integration Time Controlled by One Input Label Description Min Typ Max ti Integration time duration 5 μs – – td1 TRIG1 falling to integration period start delay – 100 ns – td2 TRIG1 rising to integration period stop delay – 1.3 μs – tt Integration period stop to read-out start delay – 1 μs – th TRIG1 hold time (pulse high duration) 1 μs – – Integration N Readout N-1 Readout N Integration N+1